1. Field of the Invention
This invention relates to the manufacture of an integrated circuit and, more particularly, to the formation of an n-channel and/or p-channel asymmetrical transistor having barrier atoms incorporated in a defined lateral area beneath a gate dielectric to enhance transistor performance.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline ("polysilicon") material over a relatively thin gate oxide. The polysilicon material and gate oxide is then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant material. If the impurity dopant material used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the source/drain dopant material is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device.
The gate conductor and adjacent source/drain areas (herein "junctions") are formed using well known photolithography and ion implant techniques. Gate conductors and source/drain regions arise in openings formed through a thick dielectric layer of what is commonly referred to as field oxide. Those openings and the transistors formed therein are termed active regions. The active regions are therefore regions between field oxide regions. Metal interconnect is routed over the field oxide to couple with the polysilicon gate conductor as well as with the junction to complete the formation of an integrated circuit.
Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single monolithic substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used. The method by which n-type dopant is used to form an n-channel device and p-type dopant is used to form a p-channel device entails unique problems associated with each device. As layout densities increase, the problems are exacerbated. Device failure can occur unless adjustments are made to processing parameters and processing steps. N-channel processing must, in most instances, be dissimilar from p-channel processing due to the unique problems of each type of device.
N-channel devices are particularly sensitive to so-called short-channel effects ("SCE"). The distance between a source-side junction and a drain-side junction is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length ("Leff"). In VLSI designs, as the physical channel becomes small, so too must the Leff. SCE becomes a predominant problem whenever Leff drops below approximately 2.0 .mu.m.
Generally speaking, SCE impacts device operation by, inter alia, reducing device threshold voltages and increasing sub-threshold currents. As Leff becomes quite small, the depletion regions associated with the source and drain areas within the junctions may extend toward one another and substantially occupy the channel area. Henceforth, some of the channel will be partially depleted without any influence of gate voltage. As a result, less gate charge is required to invert the channel of a transistor having a short Leff. Somewhat related to threshold voltage lowering is the concept of sub-threshold current flow. Even at times when the gate voltage is below the threshold amount, current between the source and drain nonetheless exist for transistors having a relatively short Leff. One method in which to control SCE is to increase the dopant concentration within the body of the device. Unfortunately, increasing dopant within the body deleteriously increases potential gradients in the ensuring device.
Increasing the potential gradients produces an additional effect known as hot-carrier effect ("HCE"). HCE is a phenomena by which the kinetic energy of the carriers (holes or electrons) is increased as they are accelerated through large potential gradients and subsequently become trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field ("Em") occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel. The electric field at the drain primarily causes electrons in the channel to gain kinetic energy and become "hot". As hot electrons travel to the drain, they lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge accumulates with time, resulting in a positive threshold shift in the NMOS transistor, or a negative threshold shift in a PMOS transistor. It is known that since hot electrons are more mobile than hot holes, HCE causes a greater threshold skew in NMOS transistors than PMOS transistors. Nonetheless, a PMOS transistor will undergo negative threshold skew if its Leff is less than, e.g., 0.8 .mu.m.
Unless modifications are made to the transistor structure, problems of sub-threshold current and threshold shift resulting from SCE and HCE will remain. To overcome these problems, alternative drain structures such as double-diffused drains (DDDs) and lightly doped drains (LDDs) must be used. The purpose of both types of structures is the same: to absorb some of the potential into the drain and thus reduce Em. The popularity of DDD structures has given way to LDD structures since DDD causes unacceptably deep junctions and deleterious junction capacitance.
A conventional LDD structure is one whereby a light concentration of dopant is self-aligned to the gate conductor followed by a heavier dopant self-aligned to the gate conductor on which two sidewall spacers have been formed. The purpose of the first implant dose is to produce a lightly doped section of both the source and drain areas at the gate edge near the channel. The second implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacer. Resulting from the first and second implants, a dopant gradient occurs at the junction between the source and channel as well as the junction between the drain and channel.
A properly defined LDD structure must be one which minimizes HCE without the expense of excessive source/drain resistance. The addition of an LDD implant adjacent the channel unfortunately adds resistance to the source/drain path. This added resistance, generally known as parasitic resistance, can have many deleterious effects. First, parasitic resistance can decrease the saturation current (i.e., current above threshold). Second, parasitic resistance can decrease the overall speed of the transistor.
The deleterious effects of decreasing saturation current and transistor speed is best explained in reference to a transistor having a source resistance and a drain resistance. The source and drain parasitic resistances are compounded by the presence of the conventional source and drain LDDs. Using a n-channel example, the drain resistance R.sub.D causes the gate edge near the drain to "see" a voltage less than VDD, to which the drain is typically connected. Similarly, the source resistance R.sub.S causes the gate edge near the source to see some voltage more than ground. As far as the transistor is concerned, its drive current along the source-drain path depends mostly on the voltage applied between the gate and source, i.e., V.sub.GS. If V.sub.GS exceeds the threshold amount, the transistor will go into saturation according to the following relation: EQU I.sub.DSAT =K/2*(V.sub.GS -V.sub.T).sup.2
where I.sub.DSAT is saturation current, K is a value derived as a function of the process parameters used in producing the transistor, and V.sub.T is the threshold voltage. Reducing or eliminating R.sub.S would therefore draw the source voltage closer to ground, thereby increasing the effective V.sub.GS. From the above equation, it can be seen that increasing V.sub.GS directly increases I.sub.DSAT While it would seem beneficial to decrease R.sub.D as well, R.sub.D is nonetheless needed to maintain HCE control. Accordingly, substantial LDD is required in the drain area. It would therefore seem beneficial to decrease R.sub.S rather than R.sub.D. This implies the need for a process for decreasing R.sub.S (source-side LDD area) while maintaining R.sub.D (drain-side LDD area).
Proper LDD design must take into account the need for minimizing parasitic resistance R.sub.S at the source side while at the same time attenuating Em at the drain-side of the channel. Further, proper LDD design requires that the injection position associated with the maximum electric field Em be located under the gate conductor edge, preferably well below the silicon surface. It is therefore desirable to derive an LDD design which can achieve the aforesaid benefits while still properly placing and diffusing Em. This mandates that the channel-side lateral edge of the LDD area be well below the edge of the gate. Regardless of the LDD structure chosen, the ensuing transistor must be one which is not prone to excessive sub-threshold currents, even when the Leff is less than, e.g., 2.0 .mu.m.
A properly designed LDD-embodied transistor which overcomes the above problems must therefore be applicable to either an n-channel transistor or a p-channel transistor. That transistor must be one that is readily fabricated within existing process technologies. In accordance with many modern fabrication techniques, it is further desirable that the improved transistor be formed having a majority carrier within the polysilicon gate of the same type as that of the junction regions (i.e., LDD implant and/or source/drain regions).